spice-sim — diodeinc/pcb Agent Skill

Mode d’emploi

Copiez la commande et examinez le paquet avant de l’installer dans votre environnement agent.
Consultez le document original pour les outils, identifiants et environnements requis.
Décrivez les entrées et le livrable souhaité ; comparez la sortie aux sources.

npx skills add https://github.com/diodeinc/pcb --skill spice-sim

Avant de commencer

L’installation n’inclut ni abonnement au modèle, ni quota API, ni accès aux fichiers.
Étoiles et installations reflètent l’activité, pas un test indépendant de qualité ou de sécurité.

Document Skill original

Rendu depuis le dépôt source en conservant titres, exemples, code, tableaux, liens et images.

Spice Simulation

Use a focused testbench such as <package>/testbench/test_<scenario>.zen for one behavior: startup, enable, a protection threshold, or current limit. Reuse an existing bench when it covers the request. Run it with pcb sim <file>.zen; a separate dummy simulation is only useful when diagnosing setup problems.

Model and testbench

The leaf component needs spice_model=SpiceModel(...). Obtain a vendor model or, when appropriate, use a behavioral model with explicit limitations. Match nets to the subcircuit's declared terminal order:

zen

Component(
    name="MyPart",
    symbol=Symbol(library="MyPart.kicad_sym"),
    pins={"VIN": VIN, "VOUT": VOUT, "GND": GND},
    spice_model=SpiceModel(
        "MyPart.lib",
        "MyPart_SUBCKT",
        nets=[VIN, VOUT, GND],
        args={},
    ),
)

Instantiate the module under test and needed loads/passives in Zener. Put sources, waveforms, analysis, and plot commands in the raw ngspice setup string of a top-level Simulation:

zen

load("@stdlib/properties.zen", "Simulation")

Simulation(
    name="SIM",
    setup="""
V_IN VIN GND DC 12
.control
  tran 10u 10m
  set hcopydevtype = svg
  hardcopy output/startup.svg v(VIN) v(VOUT)
.endc
""",
)

Adapt the source and analysis to the behavior; for example, PULSE(...) for enable timing or PWL(...) for a changing input. Write plots under testbench/output/ and inspect only the signals needed to establish the result. Distinguish a model or simulator failure from an electrical finding, and state what the model and analysis actually verify.