diodeinc/pcb

spice-sim

Add or run an ngspice-backed Zener testbench with pcb sim.

查看源码

使用方法

  1. 复制安装命令,在自己的智能体环境安装前先检查源码包。
  2. 从原始文档核对所需工具、凭据和支持的宿主。
  3. 说明输入材料与期望交付物,并对照来源检查输出。
npx skills add https://github.com/diodeinc/pcb --skill spice-sim

开始前需了解

  • 安装不包含模型订阅、API 额度或访问文件的权限。
  • 仓库星数和安装量反映活跃情况,不等于独立质量或安全测试。
仓库原始内容

按源仓库内容呈现,保留标题、案例、代码、表格、链接以及原文引用的演示图片。

Spice Simulation

Use a focused testbench such as <package>/testbench/test_<scenario>.zen for one behavior: startup, enable, a protection threshold, or current limit. Reuse an existing bench when it covers the request. Run it with pcb sim <file>.zen; a separate dummy simulation is only useful when diagnosing setup problems.

Model and testbench

The leaf component needs spice_model=SpiceModel(...). Obtain a vendor model or, when appropriate, use a behavioral model with explicit limitations. Match nets to the subcircuit's declared terminal order:

zen
Component(
    name="MyPart",
    symbol=Symbol(library="MyPart.kicad_sym"),
    pins={"VIN": VIN, "VOUT": VOUT, "GND": GND},
    spice_model=SpiceModel(
        "MyPart.lib",
        "MyPart_SUBCKT",
        nets=[VIN, VOUT, GND],
        args={},
    ),
)

Instantiate the module under test and needed loads/passives in Zener. Put sources, waveforms, analysis, and plot commands in the raw ngspice setup string of a top-level Simulation:

zen
load("@stdlib/properties.zen", "Simulation")

Simulation(
    name="SIM",
    setup="""
V_IN VIN GND DC 12
.control
  tran 10u 10m
  set hcopydevtype = svg
  hardcopy output/startup.svg v(VIN) v(VOUT)
.endc
""",
)

Adapt the source and analysis to the behavior; for example, PULSE(...) for enable timing or PWL(...) for a changing input. Write plots under testbench/output/ and inspect only the signals needed to establish the result. Distinguish a model or simulator failure from an electrical finding, and state what the model and analysis actually verify.