Intel’s wider rollout of Xeon 6+ Clearwater Forest puts a manufacturing milestone in front of a broader set of server buyers. The family launched in the second quarter of 2026; ServeTheHome reports that production subsequently expanded beyond the earliest hyperscale customers. Four models cover 144–288 efficiency cores, but the flagship is not automatically the best purchase. All share major platform resources, so adding cores also changes how much bandwidth, cache and power supports each one.
The ServeTheHome SKU analysis therefore raises a more useful question than which model has the largest number. Does the application scale across hundreds of independent cores, or does it run out of memory bandwidth, licensed-core budget or latency headroom first? The answer also determines whether Intel’s density and manufacturing story becomes an operating-cost advantage.
One platform, four resource balances
Intel’s Clearwater Forest catalog lists the 6990E+ with 288 cores, 576MB cache and 450W thermal design power; the 6980E+ with 264 cores, 528MB and 400W; the 6970E+ with 192 cores, 480MB and 400W; and the 6960E+ with 144 cores, 432MB and 330W. These are listed processor envelopes, not measurements of a loaded server at the wall.
Every model uses E-cores, emphasizing throughput density and efficiency rather than maximum single-thread speed. All support two sockets, 12 DDR5 memory channels and 96 PCIe lanes. MRDIMM support combines data from two memory ranks to increase transfer rates, with speeds up to DDR5-8000 in suitable configurations. Buyers do not need the top model simply to unlock those channels, socket support, accelerators or energy-reporting features.
Application Energy Telemetry is available throughout the family. Intel describes hardware-based attribution to workloads, containers, virtual machines, applications and individual software threads, potentially helping placement decisions and exposing work that spends energy waiting on memory or I/O. That is finer-grained attribution, not a replacement for measuring total system energy.
The manufacturing design is significant in its own right. Clearwater Forest is Intel’s first data-center processor using Intel 18A compute tiles, with RibbonFET transistors and backside power delivery. Foveros Direct connects stacked silicon through dense interconnects. The package uses 12 compute tiles, three active base tiles, two I/O tiles and 12 embedded interconnect bridges. Volume experience with this combination can inform later server designs; sustained availability, not the process name alone, will demonstrate production execution.
Fewer cores can mean more resources per thread
The 6990E+ gives each core 2MB of last-level cache. The 6970E+ raises that to 2.5MB and the 6960E+ to 3MB. The 6980E+ retains 2MB per core while reducing the count from 288 to 264. The lower two models therefore differ from the flagship in more than aggregate compute capacity: software that cannot scale cleanly to 288 cores has more supporting resources per core.
Under the stated assumption of twelve DDR5-8000 MRDIMM channels, theoretical bandwidth per core is about 2.67GB/s for the flagship and 5.34GB/s for the 144-core model. Halving the cores doubles that arithmetic allocation without changing the memory subsystem. It does not promise twice the application speed. Access patterns, compiler behavior, data placement and non-uniform memory access all affect realized bandwidth and contention.
Frequency is another distinction. The upper pair share a 3.2GHz maximum turbo, while the 6970E+ has a 2.3GHz base and the 6960E+ a 2.4GHz base. ServeTheHome reports 3.0GHz all-core turbo for the 144-core part at its listed power. Maximum turbo under limited-core conditions is not the sustained speed of hundreds of busy cores. The 6960E+ returns to the previous Sierra Forest flagship’s 144-core count but raises cache to 432MB.
Those differences suggest different starting points, not proven winners for every application. Stateless web services, content delivery, microservices, lightweight containers and dense VM hosting can use the flagship’s parallel pool. Memory-sensitive databases, analytics, network processing and imperfectly scaling services may value the 6960E+ resources. The 192-core 6970E+ offers one-third more cores than the 144-core model with more cache per core than the flagship; the 264-core 6980E+ depends more on upper-tier power limits, availability and workload behavior.
Power profiles alter the comparison, not the energy question
Intel Speed Select Technology lets supported parts use defined power/performance profiles. Both upper models support reduced-power configurations. The 6990E+ can move from 450W to 330W, with reported all-core turbo falling from 2.8GHz to 2.4GHz: approximately 14% less frequency and 27% less TDP. The same processor can emphasize maximum throughput or fit a tighter socket budget without a different CPU purchase.
At 330W, the 288-core part works out to about 1.15 listed watts per core; the reduced-power 6980E+ is approximately 1.14W per core. The 144-core 6960E+ instead spreads its 330W envelope across half as many cores, leaving more frequency headroom. Low watts per core favors density, while higher clocks may finish poorly scaling work sooner. Neither ratio measures completed work per kilowatt-hour.
Memory, storage, networking, cooling, voltage regulation and idle behavior contribute to actual consumption. A slower task can use more total energy if longer runtime outweighs lower instantaneous power. Facilities constrained by electricity or heat removal therefore need whole-server measurements. Packing more cores into a socket is not useful if rack power and cooling cannot support the productive utilization that makes the arithmetic attractive.
Intel’s launch claims, discussed by ServeTheHome, included 2.26 times average performance and 55% better performance per watt against the 144-core Xeon 6780E. The newer flagship doubles core count and has a higher power ceiling, so aggregate improvement is not an equivalent per-core leap. Selected telecommunications comparisons claimed up to 38% lower rack power and over 60% better performance per watt. All are Intel-selected workloads and configurations, not independent evidence for every deployment.
Density premiums meet licensing and failure domains
Consolidating a fixed throughput target into fewer physical machines can reduce duplicated network, management and rack-space overhead. It also concentrates failure: losing one dense node removes more capacity. Scheduling, redundancy and recovery must match that larger failure domain. A service’s latency requirements may also make reduced-frequency profiles less attractive even when average throughput remains adequate.
The 6960E+ has the lowest processor acquisition cost and the strongest core value in Intel’s published list positioning, while the upper range charges a density premium. No specific street-price advantage follows automatically. Processor cost is only part of a server: memory, chassis, motherboard, network interfaces, storage, power supplies, cooling, software, support and operational labor can make a more expensive CPU economical if it avoids duplicate systems.
Software licensing can reverse that result. Socket-based contracts can reward maximum density; per-core licensing may charge for every enabled core whether useful or idle. Virtualization and database agreements need individual treatment. Compute, memory bandwidth, capacity, storage, network and licensing can each be the binding constraint, so a core-count ranking cannot establish total value.
Representative evaluation should measure completed work, sustained frequency and tail latency across utilization levels alongside package, memory and whole-server energy. Performance at 40% utilization can matter more than peak output when a cloud service reserves capacity for bursts and service-level objectives. AET may help attribute those patterns, but a favorable per-thread or per-core statistic remains only one part of the decision.
AMD and Arm expose gaps in the benchmark story
Against AMD EPYC 9965, Intel claims approximately 30% higher average performance per thread and a similar performance-per-thread-per-watt advantage. AMD has 192 Zen 5 cores with simultaneous multithreading, exposing 384 threads; Clearwater Forest has 288 physical E-cores and 288 threads without SMT. A thread is therefore not the same resource unit in both designs.
Tom’s Hardware’s launch coverage noted the absence of a broad aggregate socket-performance comparison. Per-thread results may inform VM sizing, licensing and latency, but do not establish which socket completes more work. SMT can improve utilization while sharing core resources; separate E-cores may offer more predictable execution for some vCPU-to-physical-core mappings. Neither wins every workload.
Xeon 6+ supports AVX2, not AVX-512 or AVX10, limiting its natural fit for scientific simulation, HPC and some vector-heavy media or analytics workloads. Intel instead supplies compression, cryptography, data movement, load balancing and in-memory analytics accelerators. Software must use them to benefit. Large selected SHA or SM3 gains should not be generalized to ordinary code.
AWS Graviton, Google Axion, Microsoft Cobalt and merchant AmpereOne create another efficiency-and-density front. Clearwater Forest aims to retain cloud-native work on familiar x86, but hyperscalers increasingly control enough software to adopt another instruction set and integrate custom Arm silicon with procurement and facility design. Intel says its product compares favorably, yet broad direct Arm benchmark coverage was missing at launch. Familiarity is an advantage, not proof of lower operating cost.
Availability must turn platform compatibility into evidence
The processors share the LGA 7529 socket family with Xeon 6900P. Existing systems reportedly can support Xeon 6+ through firmware updates when vendors validate the configuration. Practical savings depend on that qualification, cooling, power delivery, memory topology and management support, not socket name alone. Wider OEM offerings would make the rollout more than an early hyperscaler deployment.
Reproducible independent tests across all four models and power profiles remain the next performance evidence. Sustained throughput, full-system power, memory population and tail latency should accompany cloud, database, telecom, virtualization, storage, compression and cryptography results. Whether the 330W flagship retains most application throughput is more meaningful than assuming frequency and throughput fall in identical proportions.
Stable 18A supply and a broader installed base would also test Intel’s manufacturing recovery and reveal which software actually uses 288 cores. For now the lineup offers several optimization targets: maximum socket density at the top, a 192-core middle ground, and more bandwidth, cache and clock per core at 144 cores. Its value emerges only when the application bottleneck, complete system costs and independent measurements are considered together.